To gate an integral clock pulse sequence from a continuous source without distorting pulse duration and number is not a trivial task. In most cases, a simple AND gate will cause problems, see Figure 1 ...

We’ve seen a few H-bridge circuits around these parts before, and here’s another application. This time we have an Old Train ...

The push for higher performance at lower power and cost has driven the VLSI industry towards System-on-Chip (SoC) integration resulting in designs with multiple clocks. It is common to see blocks that ...