[Editor's note: Part 2 of this series shows how to optimize DSP “kernels,” i.e., inner loops. For more programming tips, see the DSP programmer’s guide.] DSP applications typically have tough ...

A hands-on introduction to parallel programming and optimizations for 1000+ core GPU processors, their architecture, the CUDA programming model, and performance analysis. Students implement various ...

In this special guest feature, James Reinders describes why roofline estimation is a great tool for code optimization in HPC. Roofline Analysis is a technique that projects a view of realism into ...

A technical paper titled “Scalable Automatic Differentiation of Multiple Parallel Paradigms through Compiler Augmentation” was published by researchers at MIT (CSAIL), Argonne National Lab, and TU ...

In this slidecast, Torsten Hoefler from ETH Zurich presents: Data-Centric Parallel Programming. The ubiquity of accelerators in high-performance computing has driven programming complexity beyond the ...

Processors recently have added explicit parallelism in the form of multiple cores, and processor road maps are showing the number of cores increasing exponentially over time. This is in addition to ...

Two Google Fellows just published a paper in the latest issue of Communications of the ACM about MapReduce, the parallel programming model used to process more than 20 petabytes of data every day on ...

HAVE computers stopped getting faster? If you looked only at the clock speeds of microprocessor chips, you might well think so. A modern PC typically has a processor running at 3.0GHz (3 billion clock ...

[Editor's note: Part 2 shows how to optimize DSP kernels (i.e., inner loops), and how to write fast floating-point and fractional code. Part 4 explains why it is important to optimize “control code,” ...

A hands-on introduction to parallel programming and optimizations for 1000+ core GPU processors, their architecture, the CUDA programming model, and performance analysis. Students implement various ...