High-speed serial interfaces such as CEI, XFP/XFI, 10-Gbit/s Ethernet, and both 4-Gbit/s and 10-Gbit/s Fibre Channel are creating demands for test equipment that can give you detailed performance ...

Signal integrity is a critical design consideration in modern electronic systems, particularly those that depend on high-speed interconnects. As data rates climb and interconnect geometries become ...

In part 1, I focused on the evolution of the eye diagram: from individual signal integrity measurements to a BER bathtub that determines eye closure or Tj at a specific BER. The downside to the BER ...

The potential causes of signal integrity problems in a device are wide ranging, including the physical layout of the design, underperforming components, and accumulative affects with multiple causes.

Double-data-rate synchronous dynamic random access memory (DDR SDRAM) physical-layer testing is a crucial step in making sure devices comply with the JEDEC specification. The ultimate goal is to ...

Connecting an application processor to a DRAM chip through a 3200 Mbps LPDDR4 interface is not any easier than routing a 2600 MHz 4G LTE antenna. While RF front ends enjoy ceramic packages and careful ...

The most different aspect between a normal lamination structure and High-Density Fan-out (HDFO) is the routing scale. That aspect is also the challenge and focus of this study. At an HDFO scale, most ...

As active devices and interconnect wires shrink and are placed closer together with the march of Moore’s Law, signal integrity is becoming a huge concern. If it is not maintained, a design’s future ...