EDN

Low-Power Synchronous FIFO Memory

The CSD43301Q5M NexFET Smart Synchronous Rectifier is a highly optimized design for secondary synchronous rectification in a high power high density DC/DC converter. This product integrates the driver ...
EDN

FIFO, handshake synchronizers a challenge for CDC analysis

Among the many verification challenges confronting system-on-chip designers these days, clock domain crossings (CDCs) rank near the top in difficulty. Two particularly troublesome CDC-related issues ...
Design-Reuse

Design Transition from Sync to Async: Design and Verification Challenges

Synchronous interfaces involve a single clock domain and are relatively easy to design. However, at times, it is advantageous and necessary to have an asynchronous interface between peripherals for ...
Design-Reuse

16950 - D16950 - Expanded UART with FIFO, hard and soft flow control, synchronous mode

The D16950 is a soft core of a Universal Asynchronous Receiver/Transmitter (UART), functionally identical to the OX16C950. It allows serial transmissi ...