ArchDaily

Logical Process in Architectural Design Office

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Design-Reuse

GLOBALFOUNDRIES Offers Enhanced 55nm CMOS Logic Process with ARM Next-Generation Memory and Logic IP Support for Low Voltage

MILPITAS, Calif., February 19, 2013 – GLOBALFOUNDRIES today announced additional enhancements to the foundry’s 55-nanometer (nm) Low-Power Enhanced (LPe) process technology platform – 55nm LPe ...
Design-Reuse

Virage Logic First to Deliver Complete Memory Compiler and Logic Library IP Portfolio for TSMC 40nm Process

SiWare Physical IP Provides Built-in Power Management Capabilities to Meet Tight Power Budgets FREMONT, Calif.-- April 07, 2008 --Virage Logic Corporation, the semiconductor industry’s trusted IP ...
EDN

A logical approach to NVM integration in SOC design

Increasingly, ICs require embedded NVM (nonvolatile memory). The popularity of consumer appliances such as MP3 players—with their associated need for digital-rights management—and security ...
Semiconductor Engineering

A brief history of logic synthesis

The notions of logic synthesis can be traced back to the early 1970s and work conducted at IBM called Logic Synthesis System (LSS). This was a rule-based transformation system. These looked for ...