EDN

Statistical Static Timing Analysis – A Better Alternative

Traditionally static timing analysis (STA) is used to verify if a CMOS digital design can meet the target speed at various process and interconnect corners. In practice, the worst-case slow or ...
EDN

Researchers call for fundamental shift in timing analysis

MONTEREY, Calif. — Calling for a new approach to the design of digital circuits, researchers at the ACM/IEEE Tau workshop here this week (Dec. 2-3) presented strong arguments for a move to statistical ...
Embedded

Static timing analysis: bridging the gap between simulation and silicon

Static Timing Analysis (STA) not only acts as a connecting link between backend and frontend design activities, but more importantly helps in bridging the gap between simulation and silicon. STA is ...
Electronic Design

Interview: Cadence's Anirudh Devgan Talks About Parallel Timing Closure Signoff

System-on-Chip (SoC) developers are creating larger and more complex solutions. Static timing analysis and closure is key to successful solution so timing sign off tools can have a significant impact ...