You don’t usually think of simulating Verilog code — usually for an FPGA — as a visual process. You write a test script colloquially known as a test bench and run your simulation. You might get some ...

SAN JOSE, Calif. — InnoLogic Systems Inc. is calling its ESP-BV the first commercial hierarchical Verilog simulator, a binary simulator that uses the company's “hierarchical compression” technology.

A key part of any analogue design flow is having models of the components for simulation. Traditional Spice models of basic components such as transistors and capacitors written in C or C++ are ...

The new Active-HDL 4.2 Standard Edition shows a 300% simulation speed improvement over the previous 4.1 version for both VHDL and Verilog designs. Additionally, for Verilog designs, Active-HDL 4.2 ...

HENDERSON, Nev.--(BUSINESS WIRE)--Aldec, Inc., a pioneer in mixed-language simulation for ASIC and FPGA devices, announced today the release of Active-HDL 8.1. The new release introduces a ...

PORTLAND, Ore.--(BUSINESS WIRE)--Oct. 3, 2001--Model Technology(TM), a Mentor Graphics company, today announced that the ModelSim® hardware description language (HDL) simulator has received Verilog ...

Faster runtime performance, real-time access to built-in Verilog simulation coverage metrics, and a unified graphical environment for waveform analysis are all ...

Without functional simulation the semiconductor industry would not be where it is today, but some people in the industry contend it hasn’t received the attention and research it deserves, causing a ...

Over the last year we’ve had several posts about the Lattice Semiconductor iCEstick which is shown below. The board looks like an overgrown USB stick with no case, but it is really an FPGA development ...

AcceLight Networks recently developed a verification environment and methodology for a complex datapath controller (DPC). To accomplish this task, AcceLight used Denali Software's MMAV and Synopsys' ...