A University of Maryland professor has a radical approach to the problem of nanometer IC variability: Put it off. By combining design optimizations with postsilicon fixes, IC yield loss can be avoided ...

SAN FRANCISCO, Calif. — The right combination of better modeling and regular IC fabrics could be the best way to resolve IC variability challenges, according to panelists at the Design Automation ...

Manual and automated IC-layout tools are integrated in the PEYE Yield Finder analysis software. The combined yield-driven, standard-cell, design optimization flow facilitates the application of design ...

There is no single solution, but there plenty of room for improvement—and lots of investment around better use of data. Equipment and tools vendors are starting to focus on data as a means of ...

To ensure success in semiconductor technology development, process engineers must set the allowed ranges for wafer process parameters. Variability must be controlled, so that final fabricated devices ...